This invention relates to integrated circuits, to monolithic integrated circuits of semiconductor devices as well as passive components, and particularly to a composite integrated circuit incorporating two or more semiconductor devices of like or unlike constructions, possibly with consequent creation of a parasitic transistor. More particularly, the invention deals with such an integrated circuit featuring provisions for preventing the conduction of the parasitic transistor, limiting current flow, or other purposes.
It has been known to integrate two or more semiconductor devices into a single microchip, with the integrated devices electrically separated from each other either by pn junction isolation or a combination of pn junction and trench isolations, as disclosed for example in Japanese Unexamined Patent Publication No. 2001-135719. The semiconductor devices are formed in and on the surface of a thin substrate of semiconductor material in planar configuration.
Let us consider a more specific example of a composite integrated circuit of two laterally-diffused, metal-oxide-semiconductor field-effect transistors (LDMOSFETs). The integrated LDMOSFET circuit includes a semiconductor substrate having a p-type region for both devices, two n-type drain regions formed on the p-type region for the respective devices, two p-type body (channel) regions formed in the respective drain regions for the respective devices, two n-type source regions formed in the respective body regions for the respective devices, and a pn separator region or a separator trench between the drain regions of the two devices.
Electrically isolated from each other via the separator region or trench, the integrated two LDMOSFETs do not normally interfere with each other. They share the p-type substrate region, however, so that the composite LDMOSFET circuit gives rise to a parasitic npn transistor composed of that p-type substrate region and the n-type drain regions of the two devices. This parasitic transistor has so far been prone to conduction as when the drain terminal coupled to the drain region of one device gains a negative potential due for example to noise. Current has flown through the parasitic transistor when the drain terminal becomes less in potential than the p-type substrate region. Then, of course, the composite LDMOSFET circuit has not operated correctly. The same problem has manifested itself when two bipolar transistors, rather than LDMOSFETs, are integrated in a like manner, too.
Japanese Unexamined Patent Publication No. 2001-135719, supra, suggests how to disable the parasitic transistor. It teaches to make the p-type substrate region higher in impurity concentration than normal and to interpose an n−-type substrate region between the p-type substrate region and an n+-type buried layer of the collector region. This solution is objectionable for the additional manufacturing steps required for creation of the n−-type substrate region.
Japanese Unexamined Patent Publication No. 9-65571 proposes a discrete circuit for preventing the conduction of the parasitic transistor in a composite LDMOSFET circuit. The provision of the discrete anti-parasitic-transistor circuit makes the combination of this circuit and the composite LDMOSFET circuit difficult of manufacture and handling and adds to its installation space or area requirement.
The integrated composite LDMOSFET circuit has had an additional problem in its important application to a switching-mode power supply. A typical construction of the switching-mode power supply includes: (a) a transformer having a primary winding coupled to a source of DC voltage via an active switch, and a secondary winding coupled to an output rectifying and smoothing circuit for providing a DC output voltage; (b) a switch control circuit for rapidly turning the active switch on and off so as to keep the DC output voltage constant; (c) another rectifying and smoothing circuit coupled to the tertiary winding of the transformer for providing DC power needed for control purposes; and (d) a startup circuit for powering the switch control circuit from the DC source during the startup period. The startup circuit usually comprises a startup resistor for limiting the rush current during the startup period, and an LDMOSFET connected in series with the startup resistor.
Conventionally, in the switching-mode power supply of the above known design, the LDMOSFET and the startup resistor have been fabricated separately. The discrete startup resistor in particular has been an impediment to reduction in both size and manufacturing cost of the switching-mode power supply.